J-K Flip-Flop
If J and K are both low then no change occurs. If J and K are both high at the clock edge then the output will toggle from one state to the other. It can perform the functions of the set/reset flip-flop and has the advantage that there are no ambiguous states. It can also act as a T flip-flop to accomplish toggling action if J and K are tied together. This toggle application finds extensive use in binary counters.
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Index Electronics concepts Digital circuits Sequential Operations J-K Flip-Flop Applications | |||||
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J-K Flip-Flop Structure
While this implementation of the J-K flip-flop with four NAND gates works in principle, there are problems that arise with the timing. The timing pulse must be very short because a change in Q before the clock pulse goes off can drive the circuit into an oscillation called "racing". Modern ICs are so fast that this simple version of the J-K flip-flop is not practical (we put one together in the lab with an available 4-NAND chip and it was very unstable against racing). The next step in making use of the versatile J-K flip-flop is to use four additional NAND gates to create the Master-Slave JK Flip Flop which has two gated SR flip flops used as latches in a way that suppresses the "racing".
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Index Electronics concepts Digital circuits Electronics Tutorials allaboutcircuits | ||||||
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Switching Example: Master-Slave J-K Flip-Flop
The Master-Slave JK Flip Flop has two gated SR flip flops used as latches in a way that suppresses the "racing" or "race around" behavior. Another way to look at this circuit is as two J-K flip-flops tied together with the second driven by an inverted clock signal. When the clock makes a positive transition the master section is triggered but the slave section is not because its clock is inverted. At a half cycle of the clock, on the downward transition, the inverted clock has a positive transition and triggers the slave section. The final output Q then tracks the output of the master section M after a half cycle of the clock.
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Index Electronics concepts Digital circuits Reference Tocci Digital Systems, p170 Digital circuits Electronics Tutorials allaboutcircuits | |||
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J-K Flip-Flop Data Transfer
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Index Electronics concepts Digital circuits Data Transfer J-K Flip-Flop Applications Reference Tocci Digital Systems, Sec 5-9, 5-17 | |||||
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J-K Flip-Flop Instability or "Racing"
For this version of the J-K flip-flop under the input conditions J=K=1 the toggling would be enabled anytime the clock has value 1, and the toggling rate would be determined by the propagation delay around the circuit. The value of the output at any time would not be predictable from the clock state. This is called "racing" or the "race-around condition". This uncontrolled toggling can be suppressed by using the master-slave arrangement where the transmission of the J value to the output is delayed by half a clock cycle and not immediately fed back to the input side.
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Index Electronics concepts Digital circuits Data Transfer J-K Flip-Flop Applications References Tocci Digital Systems, Sec 5-9, 5-17 ECE Turorials/ | ||||||
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